This is historical information of device classes implemented in SpecBoardInterface device server.
Use this link to find the valid information.
Development status:
New development
Information status: Updated
Contact:
Class Description
The Simple PCIe FMC carrier (SPEC) board is a FPGA based board with SFP connector and PCIe interface (throw the Gennum GN4124 chip bridge). It is under CERN Open Hardware License (CERN OHL v1.2). The SPEC board can hold one FMC card for ADC, DAC, DIO... It can also be used as a standard node for the White Rabbit system. Check the web page http://www.ohwr.org/projects/spec/wiki for full documentation and sources.
- This class is a simple basic interface for the SPEC board. It allows to:
- load the FPGA bitstream
- read/write registers of the user and gn4124 cores.
- You will need the libspec library to build and run this class:
- git clone git@ohwr.org:fmc-projects/spec/spec-sw.git
- cd spec-sw/tools
- make
- libspec.a and libspec.so are available
Families: Acquisition
Key words:
Platform: Unix Like
Language: Cpp
License: GPL
Contact:
Hardware
Manufacturer: none
Bus: PCI Express
Class interface
Attributes:
| Name | Description |
|---|---|
| barAreaScalar: DevShort | This is the PCIe BAR area on which you want read/write registers. BAR0 :FPGA Whishbone bus registers. Access internal FPGA embedded system. BAR4 :GN4124 control registers. Access system control as boot mode or loading FPGA bitstream. |
| bitfileScalar: DevString | Path of the bitstream to load in the FPGA. |
| readAddressScalar: DevULong | Address of the register to read |
| writeAddressScalar: DevULong | Address of the register to write |
| readValueScalar: DevULong | Value read at readAddress |
| writeValueScalar: DevULong | Value to write at writeAddress |
| sizeReadBlockScalar: DevULong | Size of the register block to read (number of registers to read). |
| readRegisterBlockSpectrum: DevULong | This spectrum contains the values of a block of registers. The block starts at address readAddress and reads next registers until sizeReadBlock is reached. |
Commands:
| Name | Description |
|---|---|
| StateInput: DevVoid Output: State Device state |
This command gets the device state (stored in its device_state data member) and returns it to the caller. |
| StatusInput: DevVoid Output: ConstDevString Device status |
This command gets the device status (stored in its device_status data member) and returns it to the caller. |
| ReadRegisterInput: DevVoid Output: DevVoid |
Read a register of the barArea (whishbone or gn4124) at the address readAddress (barArea base_address + offset). Registers are 32 bits wide. |
| ReadRegisterBlockInput: DevVoid Output: DevVoid |
Read a block of registers in the barArea (whishbone or gn4124). The block starts at the address readAddress (barArea base_address + offset) and reads next registers until sizeReadBlock is reached. Registers are 32 bits wide. |
| WriteRegisterInput: DevVoid Output: DevVoid |
Write writeValue in a register of the barArea (whisbone or gn4124) at the address writeAddress (barArea base_address + offset). Registers are 32 bits wide. |
| LoadBitstreamInput: DevVoid Output: DevVoid |
Load the bitstream bitfile in the FPGA. The bitfile must be the full path (/full/path/bitstream.bit) of the bitstream. The barArea attribute is ignored because this command obviously uses the BAR4 area dedicated to the GN4124 for programming the FPGA. |
Pipes:
Properties:
Updated:
The device class has been updated.
You are looking at this version now.
19 Jan 2017, Piotr Goryl
Updated:
The device server has been updated.
You can see previous version here .
3 Jan 2017, Piotr Goryl
Created:
The device server has been added to catalogue.